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d a t a sh eet preliminary speci?cation supersedes data of 2004 jun 24 2004 oct 04 integrated circuits pnx3000 analog front end for digital video processors
2004 oct 04 2 philips semiconductors preliminary speci?cation analog front end for digital video processors pnx3000 contents 1 features 2 general description 3 ordering information 4 quick reference data 5 block diagram 6 pinning 7 functional description 7.1 vision if 7.2 dtv if 7.3 sound if 7.4 cvbs/yc source selector 7.5 rgb/ypbpr source selector 7.6 video adcs and anti-alias filters 7.7 audio source selectors and a to d converters 7.8 microphone inputs 7.9 clock generation, timing circuitry and black level clamping 7.10 data link transmitters 7.11 i 2 c-bus transceiver 7.12 power supply circuit 7.13 east-west interface 8i 2 c-bus specification 8.1 input control registers 8.2 output status registers 9 limiting values 10 thermal characteristics 11 quality specification 11.1 latch-up performance 12 characteristics 13 test and application information 13.1 power supply decoupling 13.2 application diagram 14 package outline 15 soldering 15.1 introduction to soldering surface mount packages 15.2 reflow soldering 15.3 wave soldering 15.4 manual soldering 15.5 suitability of surface mount ic packages for wave and reflow soldering methods 16 data sheet status 17 definitions 18 disclaimers 19 purchase of philips i 2 c components
2004 oct 04 3 philips semiconductors preliminary speci?cation analog front end for digital video processors pnx3000 1 features multi-standard vision if circuit with alignment-free pll demodulator without external components internal (switchable) time-constant for the if agc circuit dtv if circuit for gain control of digital broadcast tv signals sound if amplifier with separate agc circuit for quasi-split sound if circuit can also be used for intercarrier sound analog demodulator for am sound integrated sound trap and group delay correction video ident function detects the presence of a video signal video source selector with four external cvbs or yc inputs and two analog cvbs outputs with independent source selection for each output two linear inputs for 1f h or 2f h rgb signals with source selector; the rgb signals are converted to yuv before a to d conversion; both inputs can also be used as ypbpr input for dvd or set top box integrated anti-alias filters for video analog to digital converters (adcs) four 10-bit video adcs for the conversion of cvbs, yc, yuv and down-mixed sound if signals up to three different a to d converted video channels are available simultaneously (e.g. cvbs, yc and yuv) audio source selector with five stereo inputs for analog audio and two microphone inputs two microphone amplifiers with adjustable gain three analog audio outputs for scart and line out with independent source selection for each output four 1-bit audio sigma delta adcs for the conversion of audio and microphone signals three serial data link transmitters for interfacing with the digital video processor at a bit rate of 594 mbit/s per data link voltage to current converter for driving external east-west power amplifier i 2 c-bus transceiver with selectable slave address and maskable interrupt output. 2 general description the pnx3000 is an analog front end for digital video processors. it contains an if circuit for both analog and digital broadcast signals, input selectors and adcs for analog video and audio signals. the digital output signals are made available via three serial data links. the ic has a supply voltage of 5 v. the supply voltage of the analog audio part can be 5 v or 8 v, depending on the maximum signal amplitudes that are required. 3 ordering information type number package name description version pnx3000hl/n3 lqfp128 plastic low pro?le quad ?at package; 128 leads; body 14 20 1.4 mm sot425-1
2004 oct 04 4 philips semiconductors preliminary speci?cation analog front end for digital video processors pnx3000 4 quick reference data notes 1. the supply voltage for the analog audio part of the ic can be 5 v or 8 v. for a supply voltage of 5 v the maximum signal amplitudes at in- and outputs are 1 v (rms). for a supply voltage of 8 v the maximum amplitudes are 2 v (rms). 2. the rgb inputs can also be used as ypbpr input. the selection is made via the i 2 c-bus. the ypbpr input sensitivity is in accordance with the dvd player specification. symbol parameter conditions min. typ. max. unit supply v p main supply voltage 4.75 5.0 5.25 v i p main supply current - 285 320 ma v cc(1asw) , v cc(2asw) audio supply voltage note 1 4.75 8.0 8.4 v i cc(asw) audio supply current note 1 - 3.5 5.0 ma input signals v i(vif)(dif)(rms) video if ampli?er sensitivity (differential; rms value) - 75 150 m v v i(dtvif)(dif)(rms) video dtv if ampli?er sensitivity (differential; rms value) - 75 150 m v v i(sif)(rms) sound if ampli?er sensitivity (rms value) - 3db - 45 tbf db m v v i(cvbs/y)(p-p) cvbs or y input voltage (peak-to-peak value) - 1.0 1.76 v v i(rgb)(b-w) rgb inputs (black-to-white value) note 2 - 0.7 1.0 v v i(y)(p-p) luminance input signal (peak-to-peak value) note 2 - 1.0 1.43 v v i(pb)(p-p) pb input signal (peak-to-peak value) note 2 - 0.7 1.0 v v i(pr)(p-p) pr input signal (peak-to-peak value) note 2 - 0.7 1.0 v video adcs b v( - 3db) - 3 db signal bandwidth 1f h mode - 9 - mhz f sample sample frequency 1f h mode - 27 - mhz res resolution - 10 - bit analog output signals v o(cvbs)(p-p) analog cvbs output voltage (peak-to-peak value) - 2.0 - v i o(tuneragc) tuner agc output current range 0 - 1ma
2004 oct 04 5 philips semiconductors preliminary speci?cation analog front end for digital video processors pnx3000 5 block diagram handbook, full pagewidth mce430 2 10 10 10 4 2 2 2 2 cvbs prim. switch cvbs/y_prim cvbs_sec cvbs0 vifin sifin dtvifin dtvifagc tuneragc dtvifpll vifpll cvbs_if cvbs1 cvbs2 cvbs/y3 c3 cvbs/y4 c4 ycomb ccomb cvbs_dtv vif pll & dtvif mixer 2 2 qss mixer & am snd demod fpc cvbsoutif 2nd sif internal dtv 1st if dtv 2nd if cvbsouta cvbsoutb 2ndsifext (fmrad) sifagc vif amp 2 sif amp if switch sndtrap & group delay video ident 2ndsif agc det 2ndsifagc switch pnx3000 1 a d vca cvbs out switch & cvbs sec. switch clp_sec clk clk yyuv u v l r l 297 mhz 297 mhz iclp clp_prim audio switch (analog out) audio switch (digital out) audio amps am ext l1 l2 l3 l4 l5 dsndr1 dsndl2 dsndr2 r1 r2 r3 r4 r5 dsndl1 linel liner scart1l scart2r ewvin ewiout rew adr scl sda irq hv_prim vaud vaudo vauds xref 13.5 or 27 mhz hv_sec clp_prim clp_sec clp_yuv scart1r scart2l voltage to current i 2 c-bus interface timing circuit divider vd2v5 rref 27 mhz 54 mhz 13.5 mhz adc clock pll datalink pll band gap ref data link 2 data link 3 mic amps mic2 mic2 mic1 mic1 r1/pr1/v1 clp_yuv am sound iclp g1/y1/y1 b1/pb1/u1 r2/pr2/v2 g2/y2/y2 b2/pb2/u2 am int rgb/yuv matrix & switch vdefl vdefls vdeflo bgdec dlink3 4 dlink2 c 10 4 a d clk iclp iclp 297 mhz data link 1 dlink1 2 dtvout a d clk 297 mhz a d a d 6.75 mhz r2/mic2/am r a d l2/mic1/pipmono a d r1/amext primary digital audio secondary digital audio a d l1/amint fig.1 block diagram.
2004 oct 04 6 philips semiconductors preliminary speci?cation analog front end for digital video processors pnx3000 6 pinning symbol pin description cvbs2 1 cvbs2 input vaudo 2 dc output voltage for supply of audio dacs in digital decoder vauds 3 sense voltage input for audio dacs supply cvbs/y3 4 external cvbs/y3 input c3 5 external chroma3 input gnd(vsw) 6 ground video switch bgdec 7 bandgap decoupling cvbs/y4 8 external cvbs/y4 input c4 9 external chroma4 input fuse 10 fused lead gnd(filt) 11 ground ?lters cvbs_dtv 12 input for cvbs encoded signal from dtv decoder rref 13 reference current input v cc(filt) 14 supply voltage ?lters (5 v) ycomb 15 y signal input from 3d comb ?lter ccomb 16 c signal input from 3d comb ?lter amext 17 external am mono input testpin3 18 test pin 3; must be left open cvbsouta 19 cvbs or y+chroma output a vdeflo 20 dc output voltage for supply of de?ection dacs in digital decoder vdefls 21 sense input voltage for de?ection dacs supply cvbsoutb 22 cvbs or y+chroma output b fuse 23 fused lead testpin2 24 test pin 2; connect to ground r1/pr1/v1 25 r input 1 of rgb signal pr input 1 of ypbpr signal or v input 1 of yuv signal g1/y1/y1 26 g input 1 of rgb signal or y input 1 of ypbpr signal or y input 1 of yuv signal b1/pb1/u1 27 b input 1 of rgb signal pb input 1 of ypbpr signal or u input 1 of yuv signal v cc(rgb) 28 supply voltage rgb matrix (5 v) gnd(rgb) 29 ground rgb matrix r2/pr2/v2 30 r input 2 of rgb signal pr input 2 of ypbpr signal or v input 2 of yuv signal g2/y2/y2 31 g input 2 of rgb signal or y input 2 of ypbpr signal or y input 2 of yuv signal b2/pb2/u2 32 b input 2 of rgb signal pb input 2 of ypbpr signal or u input 2 of yuv signal fuse 33 fused lead gnd(vadc) 34 ground video adcs v cc(vadc) 35 supply voltage video adcs (5 v) ewvin 36 east-west input voltage ewiout 37 east-west output current rew 38 east-west voltage to current conversion resistor adr 39 i 2 c-bus address selection input xref 40 xtal reference frequency input
2004 oct 04 7 philips semiconductors preliminary speci?cation analog front end for digital video processors pnx3000 fuse 41 fused lead irq 42 interrupt request output sda 43 i 2 c-bus serial data input and output scl 44 i 2 c-bus serial clock input hv_sec 45 horizontal and vertical sync input for secondary video channel hv_prim 46 horizontal and vertical sync input for primary video channel vd2v5 47 decoupling of internal digital supply voltage gnd(dig) 48 digital ground v cc(dig) 49 digital supply voltage (5 v) strobe3n 50 strobe negative data link 3 strobe3p 51 strobe positive data link 3 data3n 52 data negative data link 3 data3p 53 data positive data link 3 fuse 54 fused lead strobe2n 55 strobe negative data link 2 strobe2p 56 strobe positive data link 2 data2n 57 data negative data link 2 data2p 58 data positive data link 2 gnd(i2d) 59 ground data links strobe1n 60 strobe negative data link 1 strobe1p 61 strobe positive data link 1 data1n 62 data negative data link 1 data1p 63 data positive data link 1 v cc(i2d) 64 supply voltage data links (5 v) scart2r 65 audio output for scart2 right scart2l 66 audio output for scart2 left liner 67 audio line output right linel 68 audio line output left scart1r 69 audio output for scart1 right scart1l 70 audio output for scart1 left fuse 71 fused lead dsndr2 72 audio signal input from digital decoder right 2 dsndl2 73 audio signal input from digital decoder left 2 dsndr1 74 audio signal input from digital decoder right 1 dsndl1 75 audio signal input from digital decoder left 1 gnd(aadc) 76 ground audio adcs v cc(aadc) 77 supply voltage audio adcs (5 v) fuse 78 fused lead r4 79 right input audio 4 l4 80 left input audio 4 r3 81 right input audio 3 symbol pin description
2004 oct 04 8 philips semiconductors preliminary speci?cation analog front end for digital video processors pnx3000 l3 82 left input audio 3 r2 83 right input audio 2 l2 84 left input audio 2 r1 85 right input audio 1 l1 86 left input audio 1 gnd(2asw) 87 ground 2 audio switch v cc(2asw) 88 supply voltage 2 audio switch (audio output buffers; 5 or 8 v) vaadcref 89 decoupling of reference voltage for audio adcs vaadcn 90 0 v reference voltage for audio adcs (gnd) vaadcp 91 full scale reference voltage for audio adcs (5 v) mic2n 92 microphone input 2, negative mic2p 93 microphone input 2, positive mic1n 94 microphone input 1, negative mic1p 95 microphone input 1, positive fuse 96 fused lead gnd(1asw) 97 ground 1 audio switch v cc(1asw) 98 supply voltage 1 audio switch (audio input buffers; 5 or 8 v) sifinp 99 sound if input, positive sifinn 100 sound if input, negative sifagc 101 control voltage for sound if agc dtvifagc 102 control voltage for dtv if agc dtvifinp 103 dtv if input, positive dtvifinn 104 dtv if input, negative tuneragc 105 tuner agc output fuse 106 fused lead vifinp 107 vision if input, positive vifinn 108 vision if input, negative dtvifpll 109 output loop ?lter dtv if pll demodulator v cc(if) 110 supply voltage if circuit (5 v) vifpll 111 output loop ?lter vif pll demodulator gnd(1if) 112 ground 1 if circuit 2ndsifext 113 second sound if input 2ndsifagc 114 second sound if agc capacitor gnd(2if) 115 ground 2 if circuit dtvoutp 116 dtv output, positive dtvoutn 117 dtv output, negative v cc(sup) 118 supply voltage of supply circuit (5 v) fuse 119 fused lead cvbsoutif 120 cvbs output of if circuit gnd(sup) 121 ground of supply circuit v cc(1vsw) 122 supply voltage 1 of video switch (5 v) symbol pin description
2004 oct 04 9 philips semiconductors preliminary speci?cation analog front end for digital video processors pnx3000 cvbs0 123 cvbs0 input for cvbs from if part testpin1 124 test pin 1; connect to ground v cc(2vsw) 125 supply voltage 2 of video switch (5 v) cvbs1 126 cvbs1 input r5 127 right input audio 5 l5 128 left input audio 5 symbol pin description
2004 oct 04 10 philips semiconductors preliminary speci?cation analog front end for digital video processors pnx3000 handbook, full pagewidth mce429 pnx3000hl 2 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 101 102 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 sifagc dtvifagc sifinn sifinp v cc(1asw) gnd(1asw) fuse mic1p mic1n mic2p mic2n vaadcp vaadcn vaadcref v cc(2asw) gnd(2asw) l1 r1 l2 r2 l3 r3 l4 r4 fuse v cc(aadc) gnd(aadc) dsndl1 dsndr1 dsndl2 dsndr2 fuse scart1l scart1r linel liner scart2l scart2r vaudo cvbs2 vauds cvbs/y3 c3 gnd(vsw) bgdec cvbs/y4 c4 fuse gnd(filt) cvbs_dtv rref v cc(filt) ycomb ccomb amext testpin3 cvbsouta vdeflo vdefls cvbsoutb fuse testpin2 r1/pr1/v1 g1/y1/y1 b1/pb1/u1 v cc(rgb) gnd(rgb) r2/pr2/v2 g2/y2/y2 b2/pb2/u2 fuse gnd(vadc) v cc(vadc) ewvin ewiout rew 40 39 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 127 128 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 r5 l5 cvbs1 v cc(2vsw) testpin1 cvbs0 v cc(1vsw) gnd(sup) cvbsoutif fuse v cc(sup) dtvoutn dtvoutp gnd(2if) 2ndsifagc 2ndsifext gnd(1if) vifpll v cc(if) dtvifpll vifinn vifinp fuse tuneragc dtvifinn dtvifinp xref adr fuse irq sda scl hv_sec hv_prim vd2v5 gnd(dig) v cc(dig) strobe3n strobe3p data3n data3p fuse strobe2n strobe2p data2n data2p gnd(i2d) strobe1n strobe1p data1n data1p v cc(i2d) fig.2 pinning configuration.
2004 oct 04 11 philips semiconductors preliminary speci?cation analog front end for digital video processors pnx3000 7 functional description 7.1 vision if the if amplifier contains 3 ac-coupled control stages which have a total gain control range of more than 66 db. the video signal is demodulated by means of an alignment-free pll carrier regenerator with an internal vco. this vco is calibrated by means of a digital control circuit which uses the external crystal frequency as a reference. the frequency setting for the various standards (33.4 mhz, 33.9 mhz, 38 mhz, 38.9 mhz, 45.75 mhz and 58.75 mhz) is realised via the i 2 c-bus. to improve performance for phase modulated carrier signals the control speed of the pll can be increased by setting bit ffi. the afc output is generated by the digital control circuit of the if pll demodulator and can be read via the i 2 c-bus. for fast search tuning systems the window of the afc can be increased with a factor of three with bus bit afw. the agc-detector operates on top sync or top white level. the demodulation polarity is switched via the i 2 c-bus. the agc detector capacitor is integrated. the time-constant can be chosen via i 2 c-bus bits agc1 and agc0. the agc has also an external mode which is activated by bit agcm. in this mode the if gain is determined by an external voltage on pin dtvifagc. the ic has an integrated sound trap filter. the filter is constructed as a cascade of three separate traps, to realize sufficient suppression of the first and second sound carriers. the trap frequencies are selected via the i 2 c-bus. the ic has an integrated group delay correction filter. the filter can be switched between the pal bg curve and a flat group delay response characteristic. this has the advantage that in multi-standard receivers the video saw filter does not need to be switchable. 7.2 dtv if apart from processing analog tv signals, the if circuit can also be used to preprocess digital tv signals before they are sent to a dtv channel decoder. for this application the two modes of operation are dtv 1st if and dtv 2nd if. for both operating modes the if pll must be set to synthesizer mode. in dtv 1st if mode only the agc function of the if circuit is used, so the dtv channel decoder must be able to handle the 1st if frequency. because the agc detector operates on the down-mixed 2nd if signal, it is still important to program a valid frequency for the if vco. it is recommended to set the frequency of the vco to a value that is approximately 4 mhz higher than the incoming 1st if centre frequency. in dtv 2nd if mode the 2nd if signal is obtained by down-mixing the incoming dtv if signal with the if vco signal. the low-pass filtered dtv 2nd if signal is available as a differential signal at the dtv output. this signal may have a maximum bandwidth of 10 mhz. the vco frequency is programmed via the i 2 c-bus in steps of 250 khz. in dtv mode the agc time constant is determined by a capacitor on pin dtvifagc. there are two agc modes: internal and external. in the internal agc mode the gain is controlled by an internal agc detector. the external agc mode is activated by bit agcm. in this mode the appropriate agc pin is used as input, so that the if gain can be controlled by the dtv channel decoder. the if pll has two pins for connection of the pll loop filters, one for analog tv and one for dtv. this allows each loop filter to be optimized for its application. 7.3 sound if the pnx3000 has a separate sound if input to enable quasi-split sound applications. the sound if amplifier is similar to the vision if amplifier and has a gain control range of about 55 db. the agc detector measures the average level of the am or fm sif carrier and ensures a constant signal amplitude for the am demodulator and quasi-split sound (qss) mixer. the single reference qss mixer is realised by a multiplier. in this multiplier the sif signal is converted to the intercarrier frequency by mixing it with the regenerated picture carrier from the video if vco. with this system a high performance stereo sound processing can be achieved. for applications without a sif saw filter the ic can also be used in intercarrier mode. in this mode the composite video signal from the vif amplifier is fed to the qss mixer and converted to the intercarrier frequency. am sound demodulation is realised in the analog domain by the qss mixer. the modulated sif signal is multiplied in phase with the limited sif signal. the demodulator output signal is low-pass filtered for suppression of the carrier harmonics. the demodulated am signal can be digitized by one of the audio adcs. the qss mixer can also be used for down-mixing an fm radio if signal to an intercarrier frequency, so that it can be demodulated by the digital decoder. the if pll must be set to synthesizer mode in this case. the preferred solution is to supply the fm radio signal via a
2004 oct 04 12 philips semiconductors preliminary speci?cation analog front end for digital video processors pnx3000 separate saw or ceramic filter to the dtv input of the pnx3000. the reason is that the selectivity of a saw filter for tv sound is not sufficient for fm radio and, if the sif input is used, no tuner agc information is available. for high performance fm radio it is recommended that a 10.7 mhz fm radio if signal is supplied to the external 2nd sif input. in this case the if signal must be filtered by an external bandpass filter, that also functions as an anti-alias filter. the low-pass filter before the 2nd sif adc must be bypassed by setting bus bit slpm. the ic includes a separate agc circuit for the 2nd sif signal. this agc is needed for intercarrier sound applications and when an external sound if signal is supplied to the 2nd sif input. the agc amplifier is preceded by a second order high-pass filter for suppression of video signal components. the agc time constant is determined by an external capacitor. 7.4 cvbs/yc source selector the video input selector consists of four independent source selectors, that can select between the cvbs signal coming from the if part and four external cvbs signals. two of the external cvbs inputs can also be used as yc input. one selector is used to select the signal for of the primary video channel. a second selector selects the cvbs or yc signal for the secondary channel. the third and fourth selectors are used to select analog outputs cvbs a and b, which can be used for scart or line output. the primary channel can be a cvbs or yc signal. if a yc signal is selected for the secondary channel or for the external cvbs outputs a or b, the luminance and chrominance signals are added to obtain a cvbs signal. the ic has an extra yc input for connection of a 3d comb filter. the comb signal can only be selected for the primary video channel. the input pin cvbs_dtv allows an analog cvbs signal derived from a digital broadcast (mpeg) signal to be recorded with an analog vcr. this signal cannot be selected for the primary video channel. the video identification circuit detects the presence of a video signal on the cvbs_if input (pin cvbs0). the identification output is normally used to detect transmitters during search tuning and can be read via the i 2 c-bus. the circuit can also be used to monitor the selected primary cvbs or yc signal. either mode is selected by bit vim. 7.5 rgb/ypbpr source selector the ic has two rgb inputs. both inputs can also be used as ypbpr input for connecting video sources with an ypbpr output like a dvd player. the rgb inputs can also be used for fast insertion of rgb signals (for instance on screen display menus) in the primary cvbs signal. the fast insertion switch is located in the digital video processor. the rgb signals are converted to yuv before further processing. the yuv output signal is digitized by two adcs. the u and v components have half the bandwidth of the y signal, therefore the u and v signals are multiplexed and digitized by one adc. 7.6 video adcs and anti-alias ?lters the pnx3000 contains four video adcs for analog and digital video broadcast signals. the clock frequency for the adcs is either 27 mhz or 54 mhz. two analog signals can be multiplexed at the input of one adc. then the clock frequency of the adc is 54 mhz and the sample frequency of each channel is 27 mhz. the video adcs are 10-bit folding adcs. the sample frequency for standard 1f h video signals is 27 mhz. for the yuv channel the sample frequency of the u and v components is half the sample frequency of the y signal. for 2f h ypbpr or rgb input signals (for instance 480p or 1080i atsc signals), the frequency that is used to sample the yuv signals is twice as high as for 1f h signals. the sample frequency is 54 mhz for y and 27 mhz for u and v. the high sample frequency requires two data links to transport the video data to the digital video processor. the anti-alias filters before the adcs limit the signal bandwidth to prevent aliasing effects. the filters for yuv can be bypassed by means of two separate bits: bit bpy for the y filter and bit bpuv for the u and v filters. this enables the use of external anti-alias filters with increased bandwidth for 2f h , rgb or ypbpr input signals. table 1 shows the signal bandwidths and sample rates for the various types of video signals. table 2 shows which video signals are sent to the digital video processor for both data link modes.
2004 oct 04 13 philips semiconductors preliminary speci?cation analog front end for digital video processors pnx3000 table 1 overview of anti-alias ?lter bandwidths and video signal sample rates. signal type signal component signal band - 1.0 db (mhz) signal band - 3.0 db (mhz) sample frequency (mhz) cvbs 8 9 27 yc y 8 9 27 c8927 yuv 1f h y8927 u 4 4.5 13.5 v 4 4.5 13.5 yuv 2f h y 161854 u8927 v8927 dtv - 10 12 - 2nd sif - 8927 7.7 audio source selectors and a to d converters the pnx3000 contains two different audio source selectors. the first selector selects which audio signals are routed to the audio adcs for further processing in the digital domain. the two microphone inputs are also connected to this selector. the selector has two outputs, a primary channel and a secondary channel. the primary audio channel is used for one stereo signal. the secondary audio channel can carry a second stereo signal, or two microphone signals, or one mono signal and one microphone signal or one mono signal and one am sound signal. the second selector selects which audio signals are fed to the analog audio outputs for scart and line out. this selector also has two stereo inputs for demodulated sound signals coming from the digital video processor. the gain from an external audio input to an analog output is 1. a supply voltage of 5 v allows input and output amplitudes of 1 v (rms) full scale. the pnx3000 has separate supply voltage pins for the audio selector circuit. to allow for input and output amplitudes of 2 v (rms) full scale, as required for compliance with the scart specification, an audio supply voltage of 8 v must be used. the audio adcs are 1-bit sigma-delta converters that operate at a clock frequency of 6.75 mhz. the audio a to d clock is synchronous with the video a to d clock, so that audio and video data can be sent over the same data links. the effective audio sample rate is ksample/s. 7.8 microphone inputs the ic has two microphone inputs. one microphone input can be used for voice control of the tv set with the help of an intelligent voice command decoder. the second input can be used for connection of a microphone for karaoke. to allow the use of microphones with different sensitivities the gain of each microphone amplifier is switchable between two values via the i 2 c-bus. 7.9 clock generation, timing circuitry and black level clamping the ic contains two pll circuits that derive the sample clock for the adcs and the bit and word clocks for the data links from an external reference frequency. the reference frequency must be a stable frequency of either 13.5 mhz or 27 mhz from a crystal oscillator. the internal reference frequency is always 13.5 mhz. if the external frequency is 27 mhz a prescaler must be activated by bus bit fxt. one pll is used to multiply the 13.5 mhz reference frequency to the 27 mhz and 54 mhz clock frequencies that are needed for the video adcs. a second pll is used to obtain the 297 mhz bit clock for the data link transmitters. a special timing circuit is used to generate the horizontal and vertical timing pulses that are needed in the if part, and also for clamping the black level of the selected video signals to a defined value at the output of the video adcs. the horizontal and vertical timing information of the primary and secondary video channels must be supplied by the digital video processor on pins hv_prim and hv_sec. the signal on these pins must consist of a f clk 128 --------- - 52.7 =
2004 oct 04 14 philips semiconductors preliminary speci?cation analog front end for digital video processors pnx3000 horizontal timing pulse that starts just before and ends just after the horizontal sync pulse of the selected video signal. to enable detection of the vertical blanking period, the horizontal pulses must be wider during a number of lines in the vertical blanking interval. the clamp signal inside the ic is generated with the help of the external horizontal timing pulse and the 13.5 mhz clock. the vertical timing information is used to disable the black level clamp, so that the black level is not disturbed by the vertical sync pulse on the video signal. the clamp pulse for the yuv channel can be derived from the primary or the secondary hv pulse, and is selected by bus bit clps. to avoid signal disturbance, it is possible to disable the black clamps when the horizontal pll in the digital video processor is not locked to the selected video signal. this is done by bus bit cmp for the primary cvbs channel and bus bit cms for the secondary cvbs channel. special attention is required when the same cvbs input is selected for primary and secondary cvbs channels. in this case the black level clamp loop is only closed for the primary cvbs input. due to internal offsets this will normally result in a deviation on the black level of the digitized secondary cvbs output. 7.10 data link transmitters three serial data links are used for transportation of the digital video and audio data coming from the adcs in the pnx3000 to the digital video processor. the use of serial data connections results in a considerable reduction in pin count and the number of connection wires that are needed between both ics. the communication between data link transmitter and data link receiver consists of two signals, a data signal and a strobe signal. the two signals together contain the data, bit-sync and word-sync information. for optimal emc performance both data and strobe are low voltage differential signals. the voltage swing on each wire is 300 mv. each data word sent over a data link consists of 44 bits: 4 video samples of 10 bits each, 2 audio bits and 2 word-sync bits. the word clock is 13.5 mhz. the data rate on each of the three data links is 594 mbit/s. table 2 shows which video signals are sent to the digital video processor for both data link modes. in the standard mode up to three video channels plus one sound if signal are digitized and transferred simultaneously over the data links. the distance between both ics that are connected via the data link must not be larger than about 10 centimetres. the two wires for each differential signal should be paired in the layout of the printed-circuit board. 7.11 i 2 c-bus transceiver the slave address of the i 2 c-bus transceiver in the pnx3000 has two possible values, selected via the adr pin. the maximum bus clock frequency is 400 khz, and the voltage swing of scl and sda can be 3.3 v or 5 v. the i 2 c-bus transceiver also has a hardwired irq output (open drain and low-active) for interruption of the microprocessor when the value of an important status bit in status byte 0 changes. the irq signal is maskable with register 0fh. 7.12 power supply circuit an internal bandgap circuit generates a stable voltage of 1.25 v. this voltage is multiplied to a reference voltage of 2.3 v, and a digital supply voltage of 2.5 v. these two voltages must be decoupled by external capacitors. a 1 / 2 v p reference voltage for the audio adcs also requires an external decoupling capacitor. the pnx3000 contains two voltage regulators to supply the sdacs that are used in the digital video processor. each regulator requires a few external components (one transistor, two resistors and a decoupling capacitor). the output voltage is adjustable between 1.25 v and 3.3 v by selection of external resistors values. 7.13 east-west interface the pnx3000 contains a voltage to current converter that serves as the interface between the voltage output of the digital video processor and the current input of the east-west stage of the vertical deflection amplifier (tda8358). the transconductance is determined by the value of an external resistor.
2004 oct 04 15 philips semiconductors preliminary speci?cation analog front end for digital video processors pnx3000 table 2 overview of data link modes 8i 2 c-bus specification the slave addresses of the ic are given in table 3. the circuit operates at clock frequencies of up to 400 khz. table 3 slave addresses (9a or 9e) bit a1 is controlled via the adr pin, when the pin is connected to ground a1 = 0 and when connected to the positive supply line a1 = 1. when this pin is left open it is connected to ground via an internal resistor. 8.1 input control registers table 4 input control registers; valid subaddresses: 00 to 0f; auto-increment mode available for subaddresses note 1. the value of this bit cannot be changed. mode application data link 1 data link 2 data link 3 video1 audio1 video2 audio2 video3 test 0 standard cvbs/y prim cl1r1y yuv u,v l2 r2 cvbs sec 2nd sif hv_p hv_s 1 yuv 2f h input y yuv l1 r1 u v l2 r2 cvbs sec 2nd sif hv_p hv_s a6 a5 a4 a3 a2 a1 a0 r/w 1 0 0 1 1 a1 1 1/0 function sub addr data byte por value (hex) d7 d6 d5 d4 d3 d2 d1 d0 vision if 0 00 afn afw ifs agcm ffi pmod agc1 agc0 00 vision if 1 01 ifon dsif dfif dtv iflh synt ssif qss 00 if pll offset 02 ifgt vai ifo5 ifo4 ifo3 ifo2 ifo1 ifo0 20 if tuner take over 03 va1 va0 tto5 tto4 tto3 tto2 tto1 tto0 20 if pll frequency 04 fxt ifa ifb ifc 000080 if synthesizer frequency 05 sf7 sf6 sf5 sf4 sf3 sf2 sf1 sf0 00 filters 06 bpuv bpy bpp gd slpm bps st1 st0 00 data link mode 07 drnd 0 0 hdtv 0 0 0 dm 00 video switches 0 08 sec3 sec2 sec1 sec0 pri3 pri2 pri1 pri0 00 video switches 1 09 vim vsw cms cmp cva3 cva2 cva1 cva0 36 video switches 2 and audio mute 0a 0 ma2 ma1 ma0 cvb3 cvb2 cvb1 cvb0 76 rgb switches 0b 0 rsel mat dvd 0 0 cmr clps 00 audio switches adc 0c mono sea2 sea1 sea0 mnm1 pra2 pra1 pra0 00 audio switches 0 0d dsg a1s2 a1s1 a1s0 mnm0 a0s2 a0s1 a0s0 00 audio switches 1 0e 0 m2g amx m1g micon a2s2 a2s1 a2s0 00 irq mask status byte 0 0f 1 (1) im6 im5 im4 im3 im2 im1 im0 80
2004 oct 04 16 philips semiconductors preliminary speci?cation analog front end for digital video processors pnx3000 table 5 afc switch table 6 afc window table 7 if sensitivity table 8 internal or external agc mode table 9 fast ?lter if pll table 10 video modulation standard table 11 if agc speed table 12 if ampli?er on/off table 13 selection of signal on analog dtv output table 14 vision if input select table 15 calibration of if pll demodulator table 16 if pll mode table 17 second sound if input table 18 sound operation afn mode 0 normal operation 1 afc not active afw afc window 0 normal 1 enlarged ifs if sensitivity 0 normal 1 reduced agcm mode 0 internal 1 external ffi condition 0 normal time constant 1 increased time constant pmod condition 0 negative modulation (fm sound) 1 positive modulation (am sound) agc1 agc0 agc speed 0 0 0.7 norm 0 1 norm 103 norm 116 norm ifon mode 0 if ampli?er not active 1 normal operation dsif dfif mode lpf active 0 0 dtv second if y 0 1 dtv ?rst if n 1 0 2nd sif internal n 1 1 spare n/a dtv mode 0 vif input 1 dtvif input iflh mode 0 calibration system active 1 calibration system not active synt mode 0 normal mode 1 synthesizer mode ssif mode 0 internal input 1 external input qss mode 0 intercarrier sound 1 quasi split sound
2004 oct 04 17 philips semiconductors preliminary speci?cation analog front end for digital video processors pnx3000 table 19 if agc operation mode note 1. gated operation improves weak signal performance. gated operation is automatically disabled if cvbs_if is not selected as primary or secondary video signal. in this situation bit iflh should be set to 1 to avoid recalibration of the if vco for white video patterns. table 20 cvbs if output signal amplitude correction for system i table 21 if pll offset adjustment table 22 cvbs if output signal amplitude table 23 if agc tuner take over table 24 external reference frequency table 25 pll demodulator frequency setting table 26 if vco synthesizer frequency (sf7 to sf0); note 1 note 1. f synth =(n+1) 250 khz; where 95 n 255. table 27 bypass uv anti-alias ?lters table 28 bypass y yuv anti-alias ?lter table 29 bypass anti-alias ?lters of primary cvbs ifgt mode 0 non gated operation 1 gated operation; note 1 vai mode pmod = 0 pmod = 1 0 no correction no correction 1 amplitude +8 % amplitude - 8% ifo5 to ifo0 (hex) control 00 tbf 20 no correction 3f tbf va1 va0 output signal amplitude pmod = 0 pmod = 1 0 0 no correction no correction 0 1 spare spare 1 0 amplitude - 5 % amplitude +5 % 1 1 amplitude +5 % amplitude - 5% tto5 to tto0 (hex) control 3f tuner take over at if input signal of 0.4 mv 00 tuner take over at if input signal of 80 mv fxt condition 0 13.5 mhz 1 27 mhz ifa ifb ifc if frequency 0 0 0 58.75 mhz 0 0 1 45.75 mhz 0 1 0 38.90 mhz 0 1 1 38.00 mhz 1 0 0 33.40 mhz 1 1 0 33.90 mhz sf7 to sf0 (decimal number) frequency 95 f = 24 mhz 255 f = 64 mhz bpuv mode 0 normal operation 1 uv anti-alias ?lters bypass bpy mode 0 normal operation 1y yuv anti-alias ?lter bypass bpp mode 0 normal operation 1 primary cvbs anti-alias ?lters bypass
2004 oct 04 18 philips semiconductors preliminary speci?cation analog front end for digital video processors pnx3000 table 30 group delay correction table 31 2nd sif lpf mode table 32 bypass anti-alias ?lters of secondary cvbs table 33 sound trap frequency table 34 data link transmitter test mode note 1. the pseudo random mode can be used for in-circuit testing of the data link connections between data link transmitter in the analog front end ic and data link receiver in the digital video processor ic. table 35 yuv 2f h clamp pulse timing table 36 data link modes; note 1 note 1. see table 2 in chapter functional description. table 37 selection of secondary video signal table 38 selection of primary video channel table 39 video ident mode table 40 if video mute gd mode 0 group delay correction bypass 1 group delay correction active slpm mode 0 2nd sif lpf active 1 2nd sif lpf bypass (for fm radio 10.7 mhz) bps mode 0 normal operation 1 secondary cvbs anti-alias ?lters bypass st1 st0 frequency 0 0 5.5 mhz 0 1 4.5 mhz 1 0 6.0 mhz 1 1 6.5 mhz drnd mode 0 normal operation 1 pseudo random test mode; note 1 hdtv mode 0 normal timing (480p signal) 1 hdtv timing (1080i signal) dm application mode 0 normal 0 1 yuv 2f h 1 sec3 sec2 sec1 sec0 selected signal 0000 cvbs_if 0001 cvbs1 0010 cvbs2 0011 cvbs3 1011y+c3 0100 cvbs4 1100y+c4 0101 cvbs_dtv other cvbs_if pri3 pri2 pri1 pri0 selected signal 0000 cvbs_if 0001 cvbs1 0010 cvbs2 0011 cvbs3 1011y+c3 0100 cvbs4 1100y+c4 1110 yc_comb other cvbs_if vim mode 0 ident coupled to cvbs_if 1 ident coupled to selected primary cvbs signal vsw mode 0 normal operation 1 cvbsoutif muted
2004 oct 04 19 philips semiconductors preliminary speci?cation analog front end for digital video processors pnx3000 table 41 clamp mode secondary cvbs channel table 42 clamp mode primary cvbs channel table 43 selection of cvbs output a table 44 mute scart2 audio output table 45 mute scart1 audio output table 46 mute line audio output table 47 selection of cvbs output b table 48 selection of rgb/yuv input table 49 rgb/yuv input mode notes 1. yuv input is an y, - (b - y) and - (r - y) input with the specification: a) y = 1.43 v (p-p); u = 1.33 v (p-p); v = 1.05 v (p-p). b) these signal amplitudes are based on a colour bar signal with 75 % saturation. 2. ypbpr input with the specification: a) y = 1.0 v (p-p); pb = 0.7 v (p-p); pr = 0.7 v (p-p). b) these signal amplitudes are based on a colour bar signal with 100 % saturation. 3. rgb input with the specification: a) r = 0.7 v b-w ; g = 0.7 v b-w ; b = 0.7 v b-w . b) these signal amplitudes are based on a colour bar signal with 100 % saturation. cms mode 0 top sync clamping mode 1 black level clamping mode cmp mode 0 top sync clamping mode 1 black level clamping mode cva3 cva2 cva1 cva0 selected signal 0000 cvbs_if 0001 cvbs1 0010 cvbs2 0011 cvbs3 1011y+c3 0100 cvbs4 1100y+c4 0101 cvbs_dtv other output muted ma2 mode 0 normal operation 1 scart2 audio output muted ma1 mode 0 normal operation 1 scart1 audio output muted ma0 mode 0 normal operation 1 line audio output muted cvb3 cvb2 cvb1 cvb0 selected signal 0000 cvbs_if 0001 cvbs1 0010 cvbs2 0011 cvbs3 1011y+c3 0100 cvbs4 1100y+c4 0101 cvbs_dtv other output muted rsel selected signal 0 rgb1 input 1 rgb2 input mat dvd mode 0 0 yuv input; note 1 0 1 ypbpr input; note 2 1 0 rgb input; note 3 1 1 spare
2004 oct 04 20 philips semiconductors preliminary speci?cation analog front end for digital video processors pnx3000 table 50 clamp mode for rgb and yuv signals table 51 clamp pulse selection for rgb and yuv signals table 52 selection of secondary audio channel note 1. selection between amint and amext must be done by digital video processor. table 53 secondary audio channel mode note 1. mono is (l + r)/2; when am is selected in table 52, mono is amint for sea[2:0] = 000 and amext for sea[2:0] = 111. a more comprehensive table can be found in the application note. table 54 selection of primary audio channel note 1. selection between amint and amext must be done by digital video processor. table 55 gain from dsnd inputs to scart outputs table 56 selection of scart1 audio output cmr mode 0 top sync clamp mode 1 black level clamp mode clps mode 0 clamp pulse of primary channel 1 clamp pulse of secondary channel sea2 sea1 sea0 selected signal 0 0 0 amint (l) and amext (r); note 1 0 0 1 l1 and r1 0 1 0 l2 and r2 0 1 1 l3 and r3 1 0 0 l4 and r4 1 0 1 l5 and r5 1 1 0 mic1 (l) and mic2 (r) 1 1 1 amext (l) and amint (r); note 1 mono mnm1 mnm0 mode 0 -- stereo; see table 52 1 0 0 mono (l) and amint (r); note 1 1 0 1 mono (l) and amext (r); note 1 1 1 0 mono (l) and mic1 (r); note 1 1 1 1 mono (l) and mic2 (r); note 1 pra2 pra1 pra0 selected signal 0 0 0 amint (l) and amext (r); note 1 0 0 1 l1 and r1 0 1 0 l2 and r2 0 1 1 l3 and r3 1 0 0 l4 and r4 1 0 1 l5 and r5 1 1 1 amext (l) and amint (r); note 1 dsg gain 0 0 db; to be used with 5 v audio supply 1 6 db; to be used with 8 v audio supply amx a1s2 a1s1 a1s0 selected signal 0000 amint 0001lr1 0010lr2 0011lr3 0100lr4 0101lr5 0110 dsnd1 0111 dsnd2 1000amext
2004 oct 04 21 philips semiconductors preliminary speci?cation analog front end for digital video processors pnx3000 table 57 selection of line audio output table 58 microphone input 2 gain table 59 microphone input 1 gain table 60 microphone ampli?ers on/off table 61 selection of scart2 audio output table 62 irq mask bits for status byte 0 note 1. the irq output is always activated if status bit por = 1. amx a0s2 a0s1 a0s0 selected signal 0000 amint 0001lr1 0010lr2 0011lr3 0100lr4 0101lr5 0110 dsnd1 0111 dsnd2 1000amext m2g gain 0low 1 high m1g gain 0low 1 high micon mode 0 microphone ampli?ers not active 1 normal operation amx a2s2 a2s1 a2s0 selected signal 0000 amint 0001lr1 0010lr2 0011lr3 0100lr4 0101lr5 0110 dsnd1 0111 dsnd2 1000amext. im6 to im0 irq output (1) 0 irq output not activated 1 irq output is activated when the corresponding status bit changes value 8.2 output status registers table 63 output status registers; subaddresses must not be sent, they are automatically incremented function sub addr data byte d7 d6 d5 d4 d3 d2 d1 d0 status byte 0 00 por msup asup rok lock vid afa afb status byte 1 01 00000dcf0agc reserved 02 00000000 status byte 3 03 id7 id6 id5 id4 id3 id2 id1 id0
2004 oct 04 22 philips semiconductors preliminary speci?cation analog front end for digital video processors pnx3000 table 64 power-on-reset table 65 main supply table 66 audio supply table 67 reference frequency table 68 if pll lock indication table 69 video identi?cation table 70 afc output table 71 data link current test table 72 tuner agc output table 73 mask version indication por condition 0 normal 1 power-down msup condition 0 main supply not ok 1 main supply ok asup condition 0 audio supply not ok 1 audio supply ok rok condition 0 reference frequency not present 1 reference frequency present lock indication 0 if pll not locked 1 if pll locked vid indication 0 no video signal detected 1 video signal detected afa afb condition 0 0 outside window; too low 0 1 outside window; too high 1 0 in window; below reference 1 1 in window; above reference dcf indication 0 data link current test ok 1 data link current test fail agc indication 0 tuner gain reduction active 1 no gain reduction of tuner id7 id6 id5 id4 id3 mask version 00000 n1a or n1b version 00001 - 00010 n1c version 00011 n1d version 00100 n1e or n1f version 00101 n2b version 00110 n3b version
2004 oct 04 23 philips semiconductors preliminary speci?cation analog front end for digital video processors pnx3000 9 limiting values in accordance with the absolute maximum rating system (iec 60134). 10 thermal characteristics note 1. the value given for the thermal resistance from junction to ambient should only be considered as an indication. most of the dissipated heat is conveyed to the ambient air through the printed-circuit board (pcb) on which the ic is mounted. the actual value of the thermal resistance depends on the number of metal layers, size and layout of the pcb, and also on the dissipation of other components on the pcb. 11 quality specification in accordance with document snw-fq-611 . 11.1 latch-up performance at t amb =70 c all pins meet the following specification: positive stress test: i trigger 3 100 ma or v trigger 3 1.5 v p(max) negative stress test: i trigger - 100 ma or v trigger - 0.5 v p(max) . symbol parameter conditions min. max. unit v p main supply voltage - 6.0 v v cc(1asw) , v cc(2asw) audio supply voltage - 9.0 v t stg storage temperature - 25 +150 c t amb ambient temperature 0 70 c t sol soldering temperature for 5 s - 260 c t j operating junction temperature - 150 c v esd electrostatic discharge voltage human body model; c = 100 pf; r = 1.5 k w pin sda - 1500 v all other pins - 2000 v machine model; c = 200 pf; r=0k w - pin sda - 150 v all other pins - 200 v symbol parameter conditions value unit r th(j-a) thermal resistance from junction to ambient in free air; note 1 30 k/w
2004 oct 04 24 philips semiconductors preliminary speci?cation analog front end for digital video processors pnx3000 12 characteristics v cc =5v; t amb =25 c; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supplies p ower supplies v p main supply voltage 4.75 5.0 5.25 v i p main supply current - 285 320 ma v cc(1asw) , v cc(2asw) audio supply voltage note 1 4.75 8.0 8.4 v i cc(asw) audio supply current note 1 - 3.5 5.0 ma v cc(sup) minimum required voltage to set status bit msup - 4.0 - v v cc(asw1) minimum required voltage to set status bit asup - 4.0 - v p tot total power dissipation - 1.45 1.70 w r eference voltages v bgdec bandgap decoupling voltage on pin bgdec 2.20 2.30 2.40 v v rref voltage on pin rref 2.19 2.30 2.41 v v vd2v5 digital supply decoupling voltage at pin vd2v5 2.35 2.50 2.65 v v por power-on reset (por) level on pin vd2v5 1.8 2.0 2.2 v v oltage regulators v audo , v deflo output voltage range note 2 1.25 - 3.30 v v auds , v defls voltage at feedback pin 1.24 1.27 1.31 v video if circuit v ideo if amplifier inputs v i(dif)(rms) input sensitivity (differential; rms value) agc set f i = 38.9 mhz - 75 150 m v f i = 45.75 mhz - 75 150 m v f i = 58.75 mhz - 75 150 m v r i(dif) input resistance (differential) note 3 - 2 - k w c i(dif) input capacitance (differential) note 3 - 3 - pf d g v gain control range 64 -- db v i(max)(dif)(rms) maximum input signal (differential; rms value) 150 -- mv
2004 oct 04 25 philips semiconductors preliminary speci?cation analog front end for digital video processors pnx3000 pll demodulator ; notes 4 and 5 d f vco free-running frequency offset of vco pll not locked; deviation from nominal setting - 500 - 0 khz f cr(pll) catching range pll without saw ?lter; referred to selected if system frequency 1 -- mhz t d(ident) delay time of identi?cation bit lock = 1 -- 20 ms v ideo amplifier output : pin cvbsoutif; note 6 v o(z) zero signal output level negative modulation; note 7 - 3.5 - v positive modulation; note 7 - 1.1 - v v o(ts) top sync level negative modulation 1.3 1.4 1.5 v v o(w) white level positive modulation - 3.4 - v v o(dem)(p-p) demodulated cvbs output signal (peak-to-peak value) recommended settings for bits va1 and va0; note 8 1.8 2.0 2.2 v d v o difference in amplitude between negative and positive modulation recommended settings for bits va1 and va0; note 8 - 015% z o(v) video output impedance - 150 250 w i bias(int) internal bias current of npn emitter follower output transistor - 0.9 - ma i source(max) maximum source current -- 1ma b v( - 3db) bandwidth of demodulated video output signal at - 3 db; before sound trap 6 9 - mhz g dif differential gain negative modulation; note 9 - 25 % positive modulation; note 9 - 35 % j dif differential phase notes 9 and 10 -- 5 deg nl vid video non-linearity note 11 -- 5% v clamp white spot clamp level - 3.8 - v n clamp noise inverter clamping level note 12 - 0.9 - v n ins noise inverter insertion level note 12 - 2.3 - v d blue intermodulation at blue notes 10 and 13 v o at 0.92 mhz or 1.1 mhz 60 66 - db v o at 2.66 mhz or 3.3 mhz 60 66 - db d yellow intermodulation at yellow notes 10 and 13 v o at 0.92 mhz or 1.1 mhz 56 62 - db v o at 2.66 mhz or 3.3 mhz 60 66 - db s/n signal-to-noise ratio notes 10 and 14 --- weighted 56 60 - db unweighted 49 53 - db d v rc residual carrier signal note 10 - 5.5 - mv symbol parameter conditions min. typ. max. unit
2004 oct 04 26 philips semiconductors preliminary speci?cation analog front end for digital video processors pnx3000 d v rc(2h) residual 2nd harmonic of carrier signal note 10 - 2.5 - mv if and tuner agc; note 15 timing of if agc mvi modulated video interference 30 % am for 1 v to 100 mv; 0 hz to 200 hz (b/g standard) -- 10 % t res response time if input signal amplitude increase of 52 db; positive and negative modulation; if agc time constant set to normal - 2 - ms if input signal amplitude decrease of 52 db negative modulation - 50 - ms positive modulation - 100 - ms tuner take over adjustment (via i 2 c-bus) v start(min)(rms) minimum starting level for tuner take over (rms value) - 0.4 0.8 mv v start(max)(rms) maximum starting level for tuner take over (rms value) 100 150 - mv tuner control output v o(max) maximum tuner agc output voltage maximum tuner gain; note 3 -- 5v v o(sat) output saturation voltage minimum tuner gain; i o =1ma -- 300 mv i o(tuneragc) tuner agc output current range 0 - 1ma i l leakage current rf agc -- 1 m a d v i input signal variation for complete tuner control 0.5 2 4 db afc output ( via i 2 c- bus ); note 16 f afc afc resolution - 2 - bits d f w window sensitivity - 125 - khz d f lw window sensitivity in large window mode - 275 - khz dtv if circuit dtv if amplifier input v i(dif)(rms) input sensitivity (differential; rms value) f i between 30 mhz and 60 mhz - 75 150 m v r i(dif) input resistance (differential) note 3 - 2 - k w symbol parameter conditions min. typ. max. unit
2004 oct 04 27 philips semiconductors preliminary speci?cation analog front end for digital video processors pnx3000 c i(dif) input capacitance (differential) note 3 - 3 - pf d g v gain control range 64 -- db v i(max)(dif)(rms) maximum input signal (differential; rms value) 150 -- mv dtv if mixer f osc oscillator frequency step size 250 khz 24 - 64 mhz n j (osc) oscillator phase noise carrier to noise ratio in dbc/hz -- 92 - db pb ll lower limit pass-band -- 1.0 mhz pb ul upper limit pass-band 10.0 -- mhz pbr pass-band ripple -- 0.5 db b sb stop band - 44 - mhz a sb stop band attenuation 40 -- db e xternal agc control d v i voltage range for full control of the ampli?er 1 - 3v z i input impedance 1 -- m w dtv output ( down - mixed output signal ) v o(dif)(p-p) differential output signal (peak-to-peak value) internal agc mode; no modulation dtv 1st if mode; f = 40 mhz - 0.68 - v dtv 2nd if mode; f = 4 mhz - 1.20 - v v o(dif)(p-p)(max) maximum allowed differential output signal (peak-to-peak value) external agc mode; note 17 dtv 1st if mode; f = 40 mhz - 0.95 - v dtv 2nd if mode; f = 4 mhz - 1.68 - v z o(dif) output impedance (differential) - 150 -w v o dc output level dtv 1st if mode - 1.15 - v dtv 2nd if mode - 3.0 - v i bias(int) internal bias current of emitter followers - 2 - ma i source(max) maximum allowed source current -- 2ma sound if circuit s ound if amplifier v i(rms) input sensitivity (rms value) - 3db - 45 tbf db m v v i(max)(rms) maximum input signal (rms value) tbf 100 - db m v r i(dif) input resistance (differential) note 3 - 2 - k w symbol parameter conditions min. typ. max. unit
2004 oct 04 28 philips semiconductors preliminary speci?cation analog front end for digital video processors pnx3000 c i(dif) input capacitance (differential) note 3 - 3 - pf d g v gain control range - 55 - db a ct(sif-vif) crosstalk attenuation between sif and vif input 50 -- db s ound if intercarrier output on dtv output ,fm modulation ; note 18 v o(dif)(rms) differential output signal amplitude (rms value) sc1; sound carrier 2 off 75 100 125 mv b - 3db bandwidth ( - 3 db) 7.5 8.5 - mhz d v r(sc)(rms) residual if sound carrier (rms value) - 2 - mv z o(dif) output impedance (differential) - 150 -w v o dc output voltage - 1.3 - v i bias(int) internal bias current of emitter followers - 2 - ma i source(max) maximum allowed source current - 2 - ma s/n w weighted s/n ratio (sc1/sc2) ratio of pc/sc1 at vision if input of 40 db or higher; note 19 black picture 53/48 58/55 - db white picture 52/47 55/53 - db 6 khz sinewave (black-to-white modulation) 44/42 48/46 - db 250 khz sine wave (black-to-white modulation) 44/25 48/30 - db sound carrier subharmonics (f = 2.75 mhz 3 khz) 45/44 51/50 - db sound carrier subharmonics (f = 2.87 mhz 3 khz) 46/45 52/51 - db am sound output ; note 20 v o(rms) af output signal amplitude (rms value) 54 % modulation 400 500 600 mv thd total harmonic distortion 54 % modulation - 0.5 1.0 % 80 % modulation - tbf 5.0 % b - 3db - 3 db af bandwidth 100 125 - khz s/n w weighted signal-to-noise ratio 54 % modulation 47 53 - db psrr power supply ripple rejection ratio 5 v main supply - 17 - db symbol parameter conditions min. typ. max. unit
2004 oct 04 29 philips semiconductors preliminary speci?cation analog front end for digital video processors pnx3000 2nd sound if agc circuit 2 nd s ound if external input d v i(rms) input voltage range (rms value) 18 - 320 mv d f i input frequency range note 21 4 - 10.7 mhz r i input resistance note 3 - 25 - k w c i input capacitance note 3 - 3 - pf 2 nd s ound if agc d g gain control range - 25 - db i ch(agc) charge current agc pin fm mode -- 12.5 m a am mode -- 2.5 m a i dch(agc) discharge current agc pin fm mode -- 50 m a am mode -- 2.5 m a overload - 1 - ma d igital output n d(p-p) decimal digital output level (peak-to-peak value) fm mode - 716 - am mode; no modulation - 358 - sound trap and group delay correction ?lter s ound trap b v( - 3db) - 3 db video bandwidth (sound trap + group delay) f sc1 = 4.5 mhz 3.90 4.00 - mhz f sc1 = 5.5 mhz 4.80 4.90 - mhz f sc1 = 6.0 mhz 5.25 5.35 - mhz f sc1 = 6.5 mhz 5.70 5.80 - mhz d v chrom(p) peaking at chroma subcarrier frequency - 1.0 2.0 db a sc1 attenuation at ?rst sound carrier f sc1 all trap frequencies 28 33 - db a sc2 attenuation at second sound carrier f sc2 f = 4.726 mhz; f sc1 = 4.5 mhz 21 27 - db f = 5.742 mhz; f sc1 = 5.5 mhz 21 27 - db f = 6.55 mhz; f sc1 = 6.0 mhz 12 18 - db f = 6.742 mhz; f sc1 = 6.5 mhz 18 24 - db g roup delay correction ; figures 6 and 7; note 22 t d(g) group delay f = 4.43 mhz; sound trap frequency 5.5 mhz; sound trap only - 180 - ns f = 4.43 mhz; sound trap frequency 5.5 mhz; sound trap plus group delay correction ?lter - 170 - ns symbol parameter conditions min. typ. max. unit
2004 oct 04 30 philips semiconductors preliminary speci?cation analog front end for digital video processors pnx3000 video switches cvbs and yc switches v i(cvbs/y)(p-p) cvbs or y input voltage (peak-to-peak value) - 1.0 1.76 v v i(cvbs/y)(clip) cvbs or y clipping level black-to-peak video - 1.33 - v i i(cvbs/y) cvbs or y input current outside clamp pulse - 0 -m a during clamp pulse - 10 - +10 m a a sup(cvbsn) suppression of non-selected cvbs input signal note 10 50 -- db v i(c)(p-p) chrominance input voltage (peak-to-peak value) 100 % colour bar; note 3 - 885 1264 mv z i(c) chrominance input impedance - 50 - k w v ideo ident function v sync(min) minimum sync pulse amplitude 70 100 140 mv t d(ident) delay time of identi?cation i 2 c-bus status bit vid = 1; after the video if agc has stabilized on a new transmitter -- 10 ms a nalog cvbs outputs : pins cvbsouta and cvbsoutb z o output impedance -- 250 w v o(p-p) output signal amplitude (peak-to-peak value) at input signal of 1.0 v (p-p) - 2.0 - v v o dc output level top sync - 0.4 - v output muted - 0.5 - v d igital outputs cvbs/y signal n d(black) decimal digital output level for black black clamp mode - 240 - n d(white) decimal digital output level for white nominal input signal - 652 - c signal n d(black) decimal digital output level for black 480 512 544 n d(p-p) decimal digital output amplitude (peak-to-peak value) nominal input level; 100 % colour bar - 520 - symbol parameter conditions min. typ. max. unit
2004 oct 04 31 philips semiconductors preliminary speci?cation analog front end for digital video processors pnx3000 rgb, ypbpr and yuv inputs analog inputs general i i input current outside clamp pulse - 0 -m a during clamp pulse - 10 - +10 m a rgb mode v i(b-w) input signal amplitude (black-to-white value) - 0.7 1.0 v ypbpr mode v i(y)(p-p) y input signal amplitude (peak-to-peak value) top sync-to-white - 1.0 1.43 v v i(pb)(p-p) pb input signal amplitude (peak-to-peak value) 100 % colour bar - 0.7 1.0 v v i(pr)(p-p) pr input signal amplitude (peak-to-peak value) 100 % colour bar - 0.7 1.0 v yuv mode v i(y) y input signal amplitude top sync-to-white - 1.43 2.04 v v i(u)(p-p) u input signal amplitude (peak-to-peak value) 100 % colour bar - 1.77 2.53 v v i(v)(p-p) v input signal amplitude (peak-to-peak value) 100 % colour bar - 1.40 2.00 v d igital outputs general d t d delay difference for the three channels note 10 - 020ns y signal n d(black) decimal digital output level for black black clamp mode - 240 - n d(white) decimal digital output level for white nominal input level - 788 - u and v signals; note 23 n d(black) decimal digital output level for black black clamp mode - 512 - n d(p-p) decimal digital output amplitude (peak-to-peak value) nominal input level; 100 % colour bar - 716 - video anti-alias ?lters cvbs, y yc ,c and 2 nd sif filters f pb( - 1db) - 1.0 db pass-band frequency - 8.0 - mhz symbol parameter conditions min. typ. max. unit
2004 oct 04 32 philips semiconductors preliminary speci?cation analog front end for digital video processors pnx3000 f pb( - 3db) - 3.0 db pass-band frequency - 9.0 - mhz f sb( - 35db) - 35 db stop band frequency - 20 - mhz t d(g) group delay at 1.0 mhz - 36 - ns at 5.0 mhz - 42 - ns e d g differential gain error note 9 - 25 % e dj differential phase error notes 9 and 10 -- 5 deg s/n signal-to-noise ratio b = 5 mhz; note 24 60 -- db y yuv filters f pb( - 1db) - 1.0 db pass-band frequency 1f h mode - 8.0 - mhz 2f h mode - 16 - mhz f pb( - 3db) - 3.0 db pass-band frequency 1f h mode - 9.0 - mhz 2f h mode - 18 - mhz f sb( - 35db) - 35 db stop band frequency 1f h mode - 20 - mhz 2f h mode - 40 - mhz t d(g) group delay at 1 mhz; 1f h mode - 36 - ns at 1 mhz; 2f h mode - 18 - ns at 5 mhz; 1f h mode - 42 - ns at 10 mhz; 2f h mode - 21 - ns s/n signal-to-noise ratio 1f h mode: b = 5 mhz 2f h mode: b = 10 mhz; note 24 60 -- db u and v filters f pb( - 1db) - 1.0 db pass-band frequency 1f h mode - 4.0 - mhz 2f h mode - 8.0 - mhz f pb( - 3db) - 3.0 db pass-band frequency 1f h mode - 4.5 - mhz 2f h mode - 9.0 - mhz f sb( - 35db) - 35 db stop band frequency 1f h mode - 10 - mhz 2f h mode - 20 - mhz t d(g) group delay at 1 mhz; 1f h mode - 72 - ns at 1 mhz; 2f h mode - 36 - ns at 2.5 mhz; 1f h mode - 84 - ns at 5 mhz; 2f h mode - 42 - ns s/n signal-to-noise ratio 1f h mode: b = 5 mhz 2f h mode: b = 10 mhz; note 24 60 -- db f ilter for dtv 2 nd if signal f pb( - 1db) - 1.0 db pass-band frequency - 10 - mhz f pb( - 3db) - 3.0 db pass-band frequency - 12 - mhz symbol parameter conditions min. typ. max. unit
2004 oct 04 33 philips semiconductors preliminary speci?cation analog front end for digital video processors pnx3000 f sb( - 35db) - 35 db stop band frequency - 44 - mhz t d(g) group delay - 22 - ns - 32 - ns s/n signal-to-noise ratio b = 10 mhz; note 25 60 -- db video analog-to-digital converters g eneral ; note 26 b v( - 3db) - 3 db signal bandwidth 1f h mode - 9 - mhz f sample sample frequency 1f h mode - 27 - mhz res resolution - 10 - bit s tatic measurements dnl differential non-linearity f clk = 54 mhz; f signal = 10 mhz - 0.7 - lsb inl integral non-linearity f clk = 54 mhz; f signal = 10 mhz - 1 - lsb d ynamic measurements thd total harmonic distortion f clk = 27 mhz; f signal = 5 mhz -- 63 - db f clk = 54 mhz; f signal = 10 mhz -- 63 - db s/n signal-to-noise ratio f clk = 27 mhz; b = 5 mhz - 58 - db f clk = 54 mhz; b = 10 mhz - 58 - db enob effective number of bits f clk = 54 mhz; f signal = 10 mhz - 9.0 - bits audio selectors lr inputs v i(max)(rms) maximum input voltage (rms value) 5 v audio supply 1.0 -- v 8 v audio supply 2.0 -- v r i input resistance 24 32 - k w g gain from lr inputs to analog outputs outputs unloaded - 0.4 0 +0.3 db a (lrn) crosstalk attenuation from non-selected inputs f = 10 khz 70 80 - db dsnd inputs for audio signals coming from digital video processor v i(max)(rms) maximum input signal amplitude (rms value) 1.0 -- v r i input resistance 24 32 - k w g gain from dsnd inputs to analog outputs 5 v audio supply; dsg = 0; outputs unloaded - 0.4 0 +0.3 db 8 v audio supply; dsg = 1; outputs unloaded 5.6 6.0 6.3 db a (dsndn) crosstalk attenuation from non-selected inputs 70 80 - db m icrophone amplifiers ; note 27 r i input resistance - 20 - k w symbol parameter conditions min. typ. max. unit
2004 oct 04 34 philips semiconductors preliminary speci?cation analog front end for digital video processors pnx3000 g low low gain bits m1g = m2g = 0 - 17 - db g high high gain bits m1g = m2g = 1 - 35 - db d f frequency range 50 - 20000 hz thd + n total harmonic distortion plus noise 1 khz input signal at 0.9 v (rms) output level - 74 - 80 - db s/n signal-to-noise ratio referred to 16 mv (rms) input level; low gain 70 76 - db referred to 16 mv (rms) input level; high gain 74 80 - db a nalog outputs v o(max)(rms) maximum output signal amplitude (rms value) 5 v audio supply 1.0 -- v 8 v audio supply 2.0 -- v z o output impedance - 500 650 w thd + n total harmonic distortion plus noise 1 khz input signal +6 dbv output level - 80 - 88 - db - 54 dbv output level; a-weighted - 36 - 40 - db s/n signal-to-noise ratio referred to 0 dbv output level; a-weighted 90 96 - db d f frequency range 20 - 20000 hz psrr power supply ripple rejection ratio 1 khz ripple frequency ripple on 5 v main supply - 43 - db ripple on 8 v audio supply - 45 - db audio analog-to-digital converters d igital audio outputs ; note 28 v i(max)(rms) maximum input voltage (rms value) 5 v audio supply 1.0 -- v 8 v audio supply 2.0 -- v thd + n total harmonic distortion plus noise 1 khz input signal +0 dbv output level -- 78 - db - 54 dbv output level; a-weighted -- 30 - db s/n signal-to-noise ratio referred to 0 dbv input level; a-weighted - 86 - db a cs channel separation 0 khz to 20 khz - 80 - db v o digital output level at 2 v (rms) input level -- 4.3 - dbfs psrr power supply ripple rejection ratio 8 v audio supply voltage; 1 khz ripple frequency ripple on 5 v main supply - 54 - db ripple on 8 v audio supply - 55 - db 5 v audio supply voltage; 1 khz ripple frequency - 18 - db symbol parameter conditions min. typ. max. unit
2004 oct 04 35 philips semiconductors preliminary speci?cation analog front end for digital video processors pnx3000 timing circuit hv input signals : pins hv_prim and hv_sec; notes 29 and 30 timing speci?cation for hv pulses coming from digital video processor; see fig.8 t (hv-sync) time between start hv pulse and start of horizontal sync pulse on cvbs/y signal 1f h tv mode - 0.6 -m s 2f h mode; hdtv = 0 - 0.3 -m s 2f h mode; hdtv = 1 - 0.3 -m s t w(hv) width of hv pulses 1f h tv mode normal lines - 72 - ck clamp disable lines - 128 - ck vsync lines - 288 - ck 2f h mode hdtv = 0 normal lines - 36 - ck clamp disable lines - 64 - ck vsync lines - 144 - ck 2f h mode; hdtv = 1 normal lines - 20 - ck clamp disable lines - 44 - ck vsync lines - 144 - ck detection of clamp disable lines t det(clamp)(dis) clamp disable detection 1f h tv mode - 80 - ck 2f h mode; hdtv = 0 - 40 - ck 2f h mode; hdtv = 1 - 24 - ck detection of vsync lines t det(vsync) vsync detection 1f h tv mode - 255 - ck 2f h mode; hdtv = 0 - 136 - ck 2f h mode; hdtv = 1 - 136 - ck internal clamp pulses t d(hv-clamp) delay between start of hv pulse and start of clamp pulse 1f h tv mode - 80 - ck 2f h mode; hdtv = 0 - 40 - ck 2f h mode; hdtv = 1 - 24 - ck t w(clamp) width of clamp pulse 1f h tv mode - 44 - ck 2f h mode; hdtv = 0 - 22 - ck 2f h mode; hdtv = 1 - 17 - ck c rystal reference frequency input : pin xref r i input resistance 25 35 45 k w c i input capacitance - 3 - pf v i(p-p) input signal amplitude (peak-to-peak value) 1 - 3.5 v symbol parameter conditions min. typ. max. unit
2004 oct 04 36 philips semiconductors preliminary speci?cation analog front end for digital video processors pnx3000 notes 1. the supply voltage for the analog audio part may have a value between 5 v and 8 v. for a supply voltage of 5 v the maximum amplitude of in- and output signals is 1 v (rms). for a supply voltage of 8 v the maximum amplitude of in- and output signals is 2 v (rms). 2. the value of the regulated voltage is determined by the external resistive voltage divider. the voltage range mentioned relates to the voltage at the emitter of the external transistor. the stability of the voltage regulator loop data link transmitters g eneral f word(clk) word clock frequency - 13.5 - mhz wl word length - 44 - bits f d data rate - 594 - mbit/s f bit(clk) bit clock frequency individual data and strobe signals - 297 - mhz o utput drivers for data and strobe signals d v o voltage swing (peak-to-peak value) individual pins; output loaded with 100 w - 0.3 - v v o(dif)(p-p) differential output voltage (peak-to-peak value) output loaded with 100 w- 0.6 - v r o output resistance -- 50 w r l load resistance connected between positive terminal and negative terminal - 100 -w east-west drive circuit: pins ewvin, ewiout and rew r i input resistance - 40 - k w d v i input voltage range 0 - 3.5 v r ew external conversion resistor note 31 - 750 -w d v o output voltage range note 31 1.0 - v cc v d i o output current range 0 - 1.2 ma i 2 c-bus control inputs and outputs sda/scl inputs and output ; note 32 v i input voltage level 0 - 5.5 v v il low-level input voltage -- 0.2 v cc v v ih high-level input voltage 0.5 v cc -- v i il low-level input current v i =0v - 0 -m a i ih high-level input current v i = 5.5 v - 0 -m a v ol low-level output voltage sda pin; i l =3ma -- 0.4 v c i input capacitance - 510pf irq output ; note 33 v ol low-level output voltage irq pin; i l = 1.5 ma -- 0.4 v v oh high-level output voltage open drain -- 5.5 v symbol parameter conditions min. typ. max. unit
2004 oct 04 37 philips semiconductors preliminary speci?cation analog front end for digital video processors pnx3000 depends on the value of the decoupling capacitor c dec on the emitter of the external transistor. recommended value is m f, with i o in ma. 3. this parameter is not tested during production and is just given as application information for the designer of the television receiver. 4. loop bandwidth b l = 60 khz (natural f n = 15 khz; damping factor d = 2; calculated with top sync level as if pll input signal level). 5. the if pll demodulator uses an internal vco (no external lc-circuit required) which is calibrated by means of a digital control circuit which uses the clock frequency of the microcontroller/teletext decoder as a reference. the required if frequency for the various standards is set via the i 2 c-bus. when the system is locked the resulting if frequency is very accurate with a deviation from the nominal value of less than 25 khz. 6. measured at pin cvbsoutif with 10 mv (rms) top sync input signal at vif input. 7. so called projected zero point, i.e. with switched demodulator. 8. the signal amplitude at the cvbsoutif output depends on the setting of bits va1 and va0. the recommended settings for negative modulation (bit pmod = 0) is va1 = va0 = 1. for positive modulation (bit pmod = 1) the settings va1 = 1 and va0 = 0 is recommended. the v o(dem)(p-p) and d v o values specified are valid if the recommended settings are used. 9. measured in accordance with the test line given in fig.3. for the differential phase test the peak white setting is reduced to 87 %: a) the differential gain is expressed as a percentage of the difference in peak amplitudes between the largest and smallest value relative to the subcarrier amplitude at blanking level. b) the phase difference is defined as the difference in degrees between the largest and smallest phase angle. 10. this parameter is not tested during production but is guaranteed by the design and qualified by means of matrix batches which are made in the pilot production period. 11. this figure is valid for the complete video signal amplitude (peak white-to-black), see fig.4. 12. the noise inverter is only active in the strong signal mode (no noise detected in the incoming signal). 13. the test set-up and input conditions are given in fig.5. measurement is done with an input signal of 10 mv (rms). 14. measured at an input signal of 10 mv (rms). the s/n is the ratio of black-to-white amplitude to the black level noise voltage (rms value); b = 5 mhz. weighted in accordance with ccir 567. 15. the time-constant of the if agc is internal and the speed of the agc can be set via bus bits agc1 and agc0. the agc response time is also dependent on the acquisition time of the pll demodulator. the values given are valid for the norm setting (agc1 = 0 and agc0 = 1) and when the pll is in lock. 16. the afc control voltage is generated by the digital tuning system of the pll demodulator. this system uses the external crystal frequency as a reference and is therefore very accurate. for this reason no maximum and minimum values are given for the window sensitivity figures. the tuning information is supplied to the tuning system via the i 2 c-bus. two bits are reserved for this function. the afc value is valid only when bit lock = 1. 17. exceeding this amplitude leads to intermodulation distortion. 18. the intercarrier sound (2nd sif) signal is not normally an analog output signal of the ic. it can be made available on the dtv output pins by setting bus bits dsif = 1 and dfif = 0. 19. the weighted s/n ratio is measured under the following conditions: a) the vision if modulator incidental phase modulation for black-to-white jumps must be less than 0.5 degrees b) qss af performance of the vision if modulator, measured with the television demodulator amf2 (audio output and weighted s/n ratio) better than 60 db (deviation 27 khz) for 6 khz sine wave black-to-white modulation c) picture-to-sound carrier ratio of the vision if modulator: pc/sc1 = 13 db (transmitter) c dec 1.5 = i o v o ------
2004 oct 04 38 philips semiconductors preliminary speci?cation analog front end for digital video processors pnx3000 d) the measurements must be carried out with the siemens saw filters g3962 for vision if and g9350 for sound if. input level for sound if 10 mv (rms) with 27 khz deviation e) the pc/sc ratio at the vision if input is calculated as the addition of the tv transmitter ratio and the saw filter pc/sc ratio. this pc/sc ratio is necessary to achieve the s/n w values as indicated. 20. the demodulated am sound signal can be made available in the analog domain on line or scart audio outputs by selecting am internal (bus bit amx = 0). 21. the frequency range of the 2nd sif channel is limited by the 2nd sif anti-alias filter. if a 10.7 mhz fm radio if signal is supplied to the external 2nd sif input; an external 10.7 mhz bandpass filter must be used; and the internal anti-alias filter must be bypassed by setting bus bit slpm = 1. 22. the cascade of sound trap and group delay correction filter compensates for the group delay pre-distortion of the bg standard, curve a (see rec. itu-r bt.470-4). the indicated values are the difference between the group delay at 4.43 mhz and the group delay at 10 khz. 23. the digitized u and v signals have the following polarity: u = +(b - y) and v = +(r - y). 24. the s/n ratio is defined as the ratio of the full scale black-to-white amplitude to the black level noise voltage (rms value). 25. the s/n ratio is defined as the ratio of the full scale peak-to-peak signal amplitude to the zero signal noise voltage (rms value). 26. the video adc is specified as a stand-alone circuit. distortion and noise of the video switch and anti-alias filters is not included. 27. the gain of the microphone amplifiers can be switched between low (17 db) and high (35 db). the low gain can be used for microphones with a sensitivity between 5 mv (rms) and 40 mv (rms) at 94 db spl. the high gain can be used for microphones with a sensitivity of less than 5 mv (rms) at 94 db spl. 28. if the audio supply voltage is 8 v; the 5 v full scale reference voltage for the audio a to d converters at pin 91 (vaadcp) is generated by the ic itself, using the internal bandgap reference. this gives the best power supply rejection ratio for the digital audio outputs. if the audio supply voltage is 5 v; pin 91 must be connected to the external 5 v supply. this results in a reduced power supply rejection ratio for the digital audio outputs. 29. signals hv_prim and hv_sec must be generated by the digital video processor using a 13.5 mhz clock. where pulse widths are specified in clock pulses, a 13.5 mhz clock is assumed (1 clock pulse is 74.1 ns). to enable detection of the vertical blanking interval, a larger pulse width is used for a number of lines during the vertical blanking period; see figs 9 and 10. 30. most timing parameters in this section are expressed in number of clock cycles, abbreviated as ck. 31. the east-west drive circuit is a voltage to current converter circuit, that requires an external conversion resistor. the open drain output transistor can only sink current. the relation between input voltage and output current is as follows: where r ew is the external conversion resistor. the voltage across the external conversion resistor is equal to v i /4. the voltage at output pin ewiout must not be lower than v i /4 + 0.25 v. the output current must not be larger than 1.2 ma. 32. the switching levels of pins sda and scl are compatible with an external signal amplitude of 3.3 v and 5 v. 33. the irq output is an open-drain output; active low. the pin irq must be loaded with a pull-up resistor. i o v i 4r ew ------------------- - =
2004 oct 04 39 philips semiconductors preliminary speci?cation analog front end for digital video processors pnx3000 mbc212 100% 92% 30% 16 % for negative modulation 100% = 10% rest carrier fig.3 video output signal. handbook, full pagewidth mbc211 100 (%) 86 72 58 44 30 64 60 56 52 48 44 40 36 32 22 12 10 26 time ( m s) fig.4 test signal waveform.
2004 oct 04 40 philips semiconductors preliminary speci?cation analog front end for digital video processors pnx3000 handbook, full pagewidth mbc213 sc cc pc - 30 db - 13.2 db - 3.2 db sc cc pc - 30 db - 13.2 db - 10 db blue yellow mce436 attenuator spectrum analyzer test circuit cc pc sc s gain setting adjusted for blue fig.5 test set-up intermodulation. input signal conditions: sc = sound carrier; cc = colour carrier; pc = picture carrier. all amplitudes with respect to top sync level. value at 0.9 mhz or 1.1 mhz 20 log v o at 3.58 mhz or 4.4 mhz v o at 0.92 mhz or 1.1 mhz -------------------------------------------------------------------------- 3.6 db + = value at 2.66 mhz or 3.3 mhz 20 log v o at 3.58 mhz or 4.4 mhz v o at 2.66 mhz or 3.3 mhz -------------------------------------------------------------------------- =
2004 oct 04 41 philips semiconductors preliminary speci?cation analog front end for digital video processors pnx3000 handbook, full pagewidth 5 f (mhz) t d(g) (ns) 225 - 25 01234 25 75 125 175 mce431 fig.6 group delay characteristic without group delay correction (sound trap: 5.5 mhz). handbook, full pagewidth 5 f (mhz) t d(g) (ns) 400 - 100 01234 0 100 200 300 mce432 fig.7 group delay characteristic with group delay correction (sound trap: 5.5 mhz).
2004 oct 04 42 philips semiconductors preliminary speci?cation analog front end for digital video processors pnx3000 handbook, halfpage mce433 cvbs_in hv pulse hgate clp 0.6 m s 5.33 m s (72 ck) 3.26 m s (44 ck) 5.92 m s (80 ck) fig.8 timing of some horizontal timing signals compared to incoming cvbs signal (1f h mode). handbook, halfpage mce434 normal lines clamp disable lines clamp disable detection clamp pulse position vsync lines vert. sync detection fig.9 horizontal timing of hv pulses (1f h mode). handbook, full pagewidth video hv pulse detected v pulse video first field second field det no norm mce435 hv pulse detected v pulse det first field second field det no norm line counter reset in digital decoder det fig.10 recommended vertical timing of incoming hv pulses (1f h mode).
2004 oct 04 43 philips semiconductors preliminary speci?cation analog front end for digital video processors pnx3000 13 test and application information 13.1 power supply decoupling for optimal thd and snr performance of the analog and digital audio channels, it is important to have stable 5 v and 8 v supply voltages for the audio part of the pnx3000. the following pins need a stable supply voltage without disturbances in the baseband audio frequency range: pins v cc(1asw) and v cc(2asw) (pins 98 and 88); the supply voltage for the analog audio switches. the supply current to both of these pins is less than 5 ma. note that this supply voltage may be 5 v or 8 v. pin vaadcp (pin 91); the 5 v full scale reference for the audio adcs. the current consumption of this pin is about 0.25 ma. this pin must only be connected to the 5 v supply if an audio supply voltage (pins v cc(1asw) and v cc(2asw) ) of 5 v is used. if an audio supply of 8 v is used, this pin must not be connected to the 5 v supply voltage. in this case the reference voltage is generated by the ic itself, and only a decoupling capacitor should be connected to this pin. pin v cc(aadc) (pin 77) is the 5 v supply voltage for the audio adcs. the supply current for this pin is about 23 ma.
2004 oct 04 44 philips semiconductors preliminary speci?cation analog front end for digital video processors pnx3000 13.2 application diagram handbook, full pagewidth mce437 1.6 k w 1.2 k w 47 k w 2.2 m f cvbs scart2 1234567 vaudo cvbs2 vauds cvbs/y3 c3 gnd(vsw) 13 rref 11 10 gnd(filt) 12 cvbs_dtv 2.2 k w 68 w 330 w 1.8 k w pnx3000 cvbs2 y3 c3 89 cvbs/y4 bgdec c4 fuse 100 nf (2) 100 nf (2) 100 nf (2) 100 nf (1) 100 nf (1) 100 nf (1) y4 c4 (1) 100 nf (1) 100 nf 100 nf (2) (2) 100 nf (2) 100 nf (1) 100 nf vdefls vdeflo cvbsouta v cc5 (1) 100 nf (1) 100 nf (1) 100 nf 100 nf (2) 10 nf 100 nf (2) cvbs1 cvbs0 v cc5 v cc5 (1) 100 nf 14 15 vcc (filt) ycomb 16 17 18 19 20 21 102 101 100 99 98 97 96 90 92 93 91 95 94 89 88 87 86 85 84 83 82 l3 ccomb amext testpin3 470 nf amext c 3d-cmb y 470 nf l3 l1 v cc5 470 nf l1 gnd(2asw) r1 470 nf r1 l2 470 nf l2 r2 470 nf r2 mic1 v cc_audio 470 nf mic1p sifinn sifinp v cc(1aasw) gnd(1asw) fuse sifagc dtvifagc 10 m f 10 m f 1 m f 82 k w 5.6 k w 10 w 100 nf 100 pf 2nd sifext 390 w 10 m f 2.2 m f 2.2 m f mic1n mic2 470 nf mic2p mic2n 2.2 m f 2.2 m f cvbs_if scart1 2.2 k w 180 w 180 w 68 w v cc(if) vifpll gnd(1if) 2ndsifext 2ndsifagc gnd(2if) dtvifpll vifinn vifinp fuse tuneragc dtvifinn dtvifinp dtv agc control saw atvifin tuneragc sifin saw dtvifin saw dtvoutp to dtv channel decoder dtvoutn gnd(sup) v cc(1vsw) testpin1 cvbs0 v cc(2vsw) cvbs1 r5 l5 fuse cvbsoutif v cc(sup) 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 121 122 123 124 125 126 127 128 119 120 118 v cc(2asw) 10 w vaadcp vaadcn vaadcref 220 w (3) b a 1.2 k w fig.11 application diagram (continued in fig.12). v cc5 = 5 v analog supply. v cc_audio = 5 v or 8 v for audio switch matrix. (1) foil or ceramic capacitor. (2) ceramic multi-layer capacitor for supply decoupling. (3) this resistor is only used when v cc_audio = 5 v, remove if v cc_audio =8v.
2004 oct 04 45 philips semiconductors preliminary speci?cation analog front end for digital video processors pnx3000 handbook, full pagewidth mce438 22 m f 4.7 m f 750 w 4.7 k w 4.7 k w 10 k w pnx3000 100 nf (2) r1/pr1/v1 g1/y1/y1 fuse cvbsoutb testpin2 r1 g1 b1/pb1/u1 v cc(rgb) gnd(rgb) b1 (1) 100 nf (1) 100 nf 470 nf (1) 100 nf (1) 100 nf (2) 100 nf r2/pr2/v2 g2/y2/y2 r2 v cc5 g2 b2/pb2/u2 fuse 100 nf (2) 100 nf (2) b2 (1) 100 nf (1) 100 nf (1) 100 nf 22 23 29 27 26 28 24 25 30 31 32 35 33 34 36 37 ewiout v audio v deflection ewvin 38 81 80 74 76 77 75 79 78 73 72 71 68 70 69 67 66 65 64 v cc(vadc) gnd(vadc) (2) 100 nf v cc5 r l r scart1 scart2 dsnd2 dsnd1 line l r l ewvin liner scart2l scart2r linel scart1r scart1l fuse gnd(aadc) v cc(aadc) dsndr2 r3 470 nf r3 l4 470 nf l4 r4 v cc5 470 nf r4 fuse 470 nf dsndl2 470 nf dsndr1 470 nf 3.3 nf 3.3 nf 3.3 nf 3.3 nf dsndl1 ewiout rew cvbs scart3 4.7 m f 2.2 k w 68 w 330 w 47 w 63 data2n strobe2p strobe2n fuse data3p data3n data2p gnd(i2d) strobe1n strobe1p data1n data1p v cc(i2d) v ccd5 v ccd5 gndd 3.3 v (13.5 or 27 mhz) gndd 62 61 60 59 58 57 56 55 54 53 52 strobe3p strobe3n 51 50 hv_prim hv_sec scl sda irq hv_prim hv_sec data link 1 data link 2 data link 3 adoc or avip scl sda irq fuse 46 45 44 43 42 41 xref fref adr 40 39 gnd(dig) 48 vd2v5 47 v cc(dig) 49 a b fig.12 application diagram (continued from fig.11). v cc5 = 5 v analog supply. v ccd5 = 5 v digital supply. gndd = digital ground. (1) foil or ceramic capacitor. (2) ceramic multi-layer capacitor for supply decoupling.
2004 oct 04 46 philips semiconductors preliminary speci?cation analog front end for digital video processors pnx3000 14 package outline unit a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec jeita mm 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 14.1 13.9 0.5 16.15 15.85 0.81 0.59 7 0 o o 0.12 0.2 0.1 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot425-1 136e28 ms-026 00-01-19 03-02-20 d (1) (1) (1) 20.1 19.9 h d 22.15 21.85 e z 0.81 0.59 d 0 5 10 mm scale b p e q e a 1 a l p detail x l (a ) 3 b c b p e h a 2 d h v m b d z d a z e e v m a x 102 103 y w m w m a max. 1.6 lqfp128: plastic low profile quad flat package; 128 leads; body 14 x 20 x 1.4 mm sot425-1 65 64 38 39 1 128 pin 1 index
2004 oct 04 47 philips semiconductors preliminary speci?cation analog front end for digital video processors pnx3000 15 soldering 15.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for fine pitch smds. in these situations reflow soldering is recommended. 15.2 re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 seconds and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 c to 270 c depending on solder paste material. the top-surface temperature of the packages should preferably be kept: below 225 c (snpb process) or below 245 c (pb-free process) C for all bga, htsson..t and ssop..t packages C for packages with a thickness 3 2.5 mm C for packages with a thickness < 2.5 mm and a volume 3 350 mm 3 so called thick/large packages. below 240 c (snpb process) or below 260 c (pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm 3 so called small/thin packages. moisture sensitivity precautions, as indicated on packing, must be respected at all times. 15.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 c or 265 c, depending on solder material applied, snpb or pb-free respectively. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 15.4 manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 c and 320 c.
2004 oct 04 48 philips semiconductors preliminary speci?cation analog front end for digital video processors pnx3000 15.5 suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your philips semiconductors sales office. 2. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 3. these transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 c 10 c measured in the atmosphere of the reflow oven. the package body peak temperature must be kept as low as possible. 4. these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 5. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 6. wave soldering is suitable for lqfp, qfp and tqfp packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 7. wave soldering is suitable for ssop, tssop, vso and vssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 8. image sensor packages in principle should not be soldered. they are mounted in sockets or delivered pre-mounted on flex foil. however, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. the appropriate soldering profile can be provided on request. 9. hot bar soldering or manual soldering is suitable for pmfp packages. package (1) soldering method wave reflow (2) bga, htsson..t (3) , lbga, lfbga, sqfp, ssop..t (3) , tfbga, vfbga, xson not suitable suitable dhvqfn, hbcc, hbga, hlqfp, hso, hsop, hsqfp, hsson, htqfp, htssop, hvqfn, hvson, sms not suitable (4) suitable plcc (5) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (5)(6) suitable ssop, tssop, vso, vssop not recommended (7) suitable cwqccn..l (8) , pmfp (9) , wqccn..l (8) not suitable not suitable
2004 oct 04 49 philips semiconductors preliminary speci?cation analog front end for digital video processors pnx3000 16 data sheet status notes 1. please consult the most recently issued data sheet before initiating or completing a design. 2. the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the latest information is available on the internet at url http://www.semiconductors.philips.com. 3. for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. level data sheet status (1) product status (2)(3) definition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn). 17 definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 18 disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2004 oct 04 50 philips semiconductors preliminary speci?cation analog front end for digital video processors pnx3000 19 purchase of philips i 2 c components purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
? koninklijke philips electronics n.v. 2004 sca76 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. philips semiconductors C a worldwide company contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales of?ces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . printed in the netherlands r24/03/pp 51 date of release: 2004 oct 04 document order number: 9397 750 14086

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